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Yes, the reason is manual work. There is no manual work involved in the designing except debugging, changing the constraints, rerunning, and all that. On the implementation side, there are very established tool flows, whether you use Cadence or Synopsys, to go through the whole process from RTL to gate to transistor to layout and then the mask. Obviously, with the advanced node, it brings some complexity and expertise that is needed. But on the verification side, massively parallel RTL coding for different blocks by distributing it, verifying each of the blocks by generating test vectors. Some of them are automated, some are directed because you need to know what the block has to do, then repeatedly run simulation, emulation, and static verification. All that to find bugs. There's no point in spending money on using the implementation licenses until you have 95%, 96% coverage of the RTL. That's why. And by the way, when we talk about AI, we will discuss how that is changing.
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This is the biggest secret in our industry. Over the last 20 to 30 years, Synopsys and Cadence have accumulated literally thousands of designs from their customers, which are not the latest versions. All our releases, whether it's VCS, Design Compiler, or Fusion, must pass 100% of all previous test cases. We have designs from AMD, like K7, K5, K7, and Intel Xeon. Startups don't have that luxury. To create a high-quality placement tool, even though they're smart and can use AI and algorithms as well as anyone else, they can't validate it until they go to the customer. That's why Synopsys and Cadence are hard to displace, even Mentor Siemens in certain areas.
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