ESD Technology Lead, Rivos

Former ESD Technical Manager at MediaTek with 12+ years in semiconductor design, leading chip-level ESD and latch-up implementation across advanced FinFET nodes (7nm/5nm/3nm) including Dimensity 5G platforms, with early exposure to Google AlphaChip-assisted design in production environments. Currently ESD Technology Lead at a RISC-V hyperscale CPU startup, working directly with TSMC on whole-chip ESD sign-off and with Siemens EDA on automated design flow optimization for AI server chips, providing current insider perspective on advanced node constraints and the evolving hyperscale chip design ecosystem.